Course Content

1.SystemVerilog for Verification

• Data Types & OOP
• Interfaces & Clocking
• Randomization & Coverage
• Concurrency & IPC

2.UVM Architecture Fundamentals

• UVM Philosophy
• Reporting & Factory
• Building the Environment

3. Advanced UVM & Scoreboarding

• Sequences & Items
• Virtual Sequences
• Data Checking

4. Modern DV & Automation

• Register Abstraction Layer (RAL)
• Next-Gen Automation
• Project Integration

5. Open-Source Projects for Hands-On Training

•  Beginner Level: UVM Fundamentals
• Intermediate Level: Standard Protocol VIPs
• Advanced Level (Capstone): RISC-V Processor Verification